1. Field of the Invention
This invention relates, generally, to semiconductor devices and methods for their fabrication, and more particularly, to methods for fabricating EEPROM devices requiring extended data retention.
2. Description of the Prior Art
State of the art memory devices include both volatile and non-volatile memory devices. Volatile memory devices are those devices that require continuous electrical power to maintain stored charge within the memory cell. To maintain data in the memory of a volatile device, the memory cells must be continually refreshed, otherwise the stored charge will dissipate and the data will be lost. In contrast, non-volatile memory devices are capable of retaining stored data even after electrical power to the device is terminated. The non-volatile memory device typically stores electrical charge on either a separate gate electrode, known as a floating-gate, or in a dielectric layer underlying a control gate electrode. Data is stored in a non-volatile memory device by changing the threshold voltage of the floating-gate transistor. For example, in an n-channel floating-gate transistor an accumulation of electrons in the floating-gate electrode creates a high threshold voltage in the transistor. The presence or absence of electrical charge, or data, within an EEPROM memory cell is determined by the presence or absence of current flow through the floating-gate transistor as voltage is applied to the control-gate electrode.
One particular type of non-volatile memory device is the flash EEPROM. Flash EEPROMs are a type of EEPROM device that provides electrical erasing capability. The term "flash" refers to the ability to erase the memory cell simultaneously with electrical pulses. In an erased state, the threshold voltage of the floating-gate transistor is low, and, upon application of a turn-on voltage to the floating-gate electrode, an electrical current will flow through the transistor. When current is sensed flowing through the floating-gate transistor, charge is present on the floating-gate, which is defined as a logic 1 state. Conversely, when there is no charge on the floating-gate electrode, and a turn-on voltage is applied to the floating gate electrode, the transistor will not turn on, hence no current flows through the transistor. The absence of current flow then is defined as a logic 0 state.
EEPROM cells have recently been extensively used in programmable logic devices (PLDs). Most conventional EEPROM memory cells are formed with three transistors: a write transistor, a read transistor, and a floating-gate transistor (also known as a sense transistor). In the PLD EEPROM memory cell, the gate electrode of the write transistor and the read transistor are connected to the same word line. Also, the read transistor and the floating-gate transistor (or sense transistor) are connected to the same data line. Thus, when the read transistor is turned on, the floating-gate transistor is effectively used as the storage cell of the EEPROM.
To program the EEPROM device, a high voltage (between 13 and 15 volts), is applied to the word line of the EEPROM memory cell, and a relatively high voltage (approximately 11 to 12 volts) is applied to the electrode gate of the write transistor. This allows the voltage applied on the bit line to be transferred to the floating-gate electrode, thus placing charge on the floating-gate electrode.
To erase the EEPROM memory cell, a voltage V.sub.cc is applied to the word line of the write transistor. Because the gate electrodes are connected by the same word line, this also causes the read transistor to turn on. Ground potential is applied to the bit line, which is connected to the drain of the read transistor, and a high voltage (between 13 to 15 volts) is applied to the source region of the floating-gate transistor. Under these voltage conditions, the high voltage applied to the source is capacitively coupled to the floating-gate electrode, which causes electrons to tunnel from the floating-gate electrode through a tunnel oxide region and into the substrate, thereby erasing the EEPROM memory cell.
Over time, the EEPROM memory cell will be written and erased repeatedly as data is stored and removed from the memory cell. Since the EEPROM memory cell relies on charge exchange between the substrate and the floating-gate electrode, considerable stress is placed on the tunnel oxide underlying the floating-gate electrode. The charge-induced stress in the tunnel oxide can cause charge trapping sites to form within the tunnel oxide. The formation of these charge trapping sites is undesirable because, once formed, electrical current can leak through the tunnel oxide layer from the floating-gate electrode to the substrate. When charge leaks off the floating-gate electrode a data error occurs in the EEPROM memory cell. Depending upon the particular function performed by the EEPROM memory cell, the data error can cause catastrophic failure in an electronic system relying upon the EEPROM memory device.
One solution to the tunnel oxide leakage problem is to form thicker oxide layers within the EEPROM device. By providing more oxide, the formation of a small number of charged trapping sites can be tolerated without deleterious current leakage in the device. While fabricating the oxide layers to greater thicknesses reduce charge leakage problems, the thicker oxide layers prevent scaling of the overall size of the EEPROM memory cell. However, scaling down (reducing component size) of transistors having large oxide thicknesses cannot be achieved due to basic device physics. Thus, conventional EEPROM memory devices requiring transistors having relatively thick oxide layers cannot effectively be scaled down to smaller overall dimensions.
Another problem associated with EEPROM devices having relatively thick oxide layers relates to programming and erasing speed. As the thickness of the oxide layers increase, especially the tunnel oxide, the time required to transfer a charge between the substrate and the floating-gate electrode also increases.
Yet another problem suffered by conventional EEPROM devices is the lack of ability to scale down the large high-voltage transistors fabricated in the peripheral regions of the device. These high-voltage transistors are necessary to perform input and output functions, and to provide high-voltage power supply functions, and the like. These transistors typically have transistor geometries, such as gate lengths, that are significantly greater than the read and write transistors within the EEPROM cells. In order to significantly reduce component size and scale the device to smaller dimensions, it is necessary to fabricate both the high-voltage transistors and the memory cell transistors to smaller dimensions. Accordingly, an improved fabrication process is necessary to provide a high-reliability EEPROM device that can be programmed and erased at high speeds and that is fully scalable to smaller dimensions.